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NJU72040
Ground Referenced Stereo Headphone Amplifier
GENERAL DESCRIPTION The NJU72040 is an audio headphone amplifier . Ground-referenced outputs eliminate output coupling capacitor. The pop noise suppression circuit removes a pop noise at the power-on and power-off. It is suitable for audio headphone amplifer application APPLICATIONS q Audio applications which have audio headphone interface FEATURES q Operating Voltage q Operating Current q q q q q Output Coupling Capacitor-less Pop Noise Suppression Circuit Gain Select C-MOS Technology Package Outline s PACKAGE OUTLINE
NJU72040V
+2.7 to +3.6V IDD=10.5mA typ. + at V =3.3V, No load, No Signal
SSOP14
BLOCK DIAGRAM
V+
inverted phase
Reg INRV+ V+
inverted phase
INL-
INL+
INR+
OUTL 32 Headphone
Pop Noise Suppression
Pop Noise Suppression
OUTR 32 Headphone V+
V+
GND
CP Bias CN Regulator
MUTE 3M
V-
GAIN 100k
REF Gain Select
Ver. 1.2E
-1-
NJU72040
PIN CONFIGURATION
1 INLINL+ OUTL V+ CP CN GAIN 7
14 INRINR+
NJU72040
OUTR GND MUTE VREF 8
No. 1 2 3 4 5 6 7
Symbol Function INLLch Inverted Input INL+ Lch Noninverted Input OUTL Lch Output V+ V+ Power Supply CP Flying Capacitor Positive Terminal CN Flying Capacitor Negative Terminal GAIN Gain Select
No. 8 9 10 11 12 13 14
Symbol REF VMUTE GND OUTR INR+ INR-
Function Reference Voltage Input V- Power Supply MUTE / Pop Noise Suppression Ground Rch Output Rch Inverted Input Rch Noninverted Input
-2-
NJU72040
ABSOLUTE MAXIMUM RATING (Ta=25C)
PARAMETER
Supply Voltage Power Dissipation Maximum Input Voltage Operating Temperature Range Storage Temperature Range
SYMBOL
V
+
RATING
+4 SSOP14 : 550 V +0.3 -40 ~ +85 -40 ~ +125
+ (Note1)
UNIT
V mW V C C
PD VIM Topr Tstg
(Note1) EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
s RECOMMENDED OPERATING CONDITIONS
(Ta=25C unless otherwise specified)
PARAMETER
Operating Voltage
SYMBOL
V
+
TEST CONDITION
MIN.
2.7
TYP.
3.3
MAX.
3.6
UNIT
V
ELECTRICAL CHARACTERISTICS
(Ta=25C, V =3.3V, f=1kHz, Vin=0.1Vrms[differential input], Gv=6.4dB, MUTE=OFF, RL=32 unless otherwise specified)
+
PARAMETER
Operating Current Input Resistance1 Input Resistance2 Voltage Gain1 Voltage Gain2 Voltage Gain3 Voltage Gain4 Maximum Output Power1 Maximum Output Power2 Maximum Output Voltage Level Mute Level Equivalent Input Noise Voltage Total Harmonic Distortion1 Total Harmonic Distortion2 Channel Separation1 Channel Separation2 Output Offset Voltage
SYMBOL
IDD Rin1 Rin2 GV1 GV2 GV3 GV4 POMAX1 POMAX2 VOMAX VMUTE VNI THD1 THD2 CS1 CS2 VOS
TEST CONDITION
No signal, No load INL-, INRINL+, INR+ Gain Terminal=Low Gain Terminal=High Gain Terminal=Low, RL=10k Gain Terminal=High, RL=10k THD=3%, RL=32 Input=Lch or Rch THD=3%, RL =32 Input=Lch and Rch THD=1%, RL=10k Rg=0 , Mute=ON Rg=0 , BW:400Hz-22kHz BW:400Hz-22kHz, RL=32 BW:400Hz-22kHz, RL=10k Rg=600 , (*1) Rg=600 , f=10kHz, (*1) Rg=0 , Gv=12.4Db, No load
MIN.
49 103 5.4 11.4 6.6 12.6 65 55 -
TYP.
10.5 61 129 6.4 12.4 7.1 13.1 80 55 2.2 -90 -100 0.08 0.007 75 65 1
MAX.
15.5 73 155 7.4 13.4 7.6 13.6 -80 -95 0.3 0.05 5
UNIT
mA k k dB dB dB dB mW mW Vrms dB dBV % % dB dB mV
(*1)OUTL(measured terminal): 20log(OUTR/OUTL) , OUTR(measured terminal): 20log(OUTL/OUTR)
CONTROL CHARACTERISTICS
(Ta=25C, V =3.3V, Gv=6.4dB, MUTE=OFF, RL=32 unless otherwise specified)
+
PARAMETER
Mute terminal High Mute terminal Low Gain terminal High Gain terminal Low
SYMBOL
MuteH MuteL GainH GainL
TEST CONDITION
Mute=OFF Mute=ON Gv=12.4dB Gv=6.4dB
MIN.
0.8 V 0 0.8 V 0
+ +
TYP.
-
MAX.
V
+ +
UNIT
V V V
0.2 V V
+
0.2 V
+
V
-3-
NJU72040
TEST CIRCUIT (IDD)
V+ INLC1=1uF
Regulator INRC10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
V+
Pop Noise Suppression Pop Noise Suppression
OUTR
A
V+
GND
(*2)
C4=1uF
CP Negative Voltage Regulator Bias
3M
MUTE
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors TEST CIRCUIT (GV1, GV2, GV3, GV4, POMAX1, VOMAX)
V+
inverted phase
Regulator INRC10=1uF
INL-
C1=1uF
INL+
C2=1uF Gv1,2,POMAX1 RL=32 Gv3,4,VOMAX RL=10k
INR+
C8=1uF
OUTL V V+
Pop Noise Suppression Pop Noise Suppression
OUTR
GND
Gv1,2,POMAX1 RL=32 Gv3,4,VOMAX RL=10k V+
(*2)
C4=1uF
CP Negative Voltage Regulator Bias
3M
MUTE
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors
-4-
NJU72040
TEST CIRCUIT (POMAX2)
V+
inverted phase
Regulator INRinverted phase
INL-
C1=1uF
C10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
RL=32
OUTR
Pop Noise Suppression Pop Noise Suppression
V V+
RL=32
GND
V+
(*2)
CP Negative Voltage Regulator Bias
MUTE 3M
C4=1uF
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors TEST CIRCUIT (VMUTE)
V+
inverted phase
Regulator INRC10=1uF
INL-
C1=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
RL=32
OUTR
Pop Noise Suppression Pop Noise Suppression
V V+
RL=32
GND
(*2)
C4=1uF
CP Negative Voltage Regulator Bias
3M
MUTE
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors
-5-
NJU72040
TEST CIRCUIT (VNI) VNI=(measurement)-Gv1
INLC1=1uF
V+
Regulator INRC10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
RL=32
OUTR
Pop Noise Suppression Pop Noise Suppression
V V+
V GND
RL=32
(*2)
C4=1uF
CP Negative Voltage Regulator Bias
3M
MUTE
V+
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors TEST CIRCUIT (THD1, THD2)
V+
inverted phase
Regulator INRC10=1uF
INL-
C1=1uF
Ex) AudioPrecision aux-0025 Filter V
THD1 RL=32 THD2 RL=10k
INL+
C2=1uF
INR+
C8=1uF
OUTL
Pop Noise Suppression Pop Noise Suppression
OUTR
V+
GND
V+
(*2)
C4=1uF
CP Negative Voltage Regulator Bias
3M
MUTE
THD1 RL=32 THD2 RL=10k
CN
V-
(*2)
C6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors (*3): Connect a low-pass filter circuit with the corner frequency of more than 20kHz in front of an analyzer for rejecting the switching noise generated from NJU72040. Otherwise, the characteristic result may change because of the switching noise.
-6-
NJU72040
TEST CIRCUIT (CS1, CS2) OUTL (measured terminal) : CS1=CS2=20log(OUTR/OUTL) OUTR (measured terminal) : CS1=CS2=20log(OUTL/OUTR)
V+
inverted phase
Regulator INRC10=1uF Rg=600
INL-
C1=1uF
INL+
C2=1uF
INR+
C8=1uF
Rg=600
OUTL
RL=32
Pop Noise Suppression Pop Noise Suppression
OUTR V GND
RL=32
V+
CP
C4=1uF
CN
Negative Voltage Regulator
Bias
3M
MUTE
V+
VC6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors TEST CIRCUIT (VOS)
V+ INLC1=1uF
Regulator INRC10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL V V+
Pop Noise Suppression Pop Noise Suppression
OUTR V GND
CP
C4=1uF
CN
Negative Voltage Regulator
Bias
3M
MUTE
V+
VC6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors
-7-
NJU72040
APPLICATION CIRCUIT (Single-end input)
V+ INLC1=1uF
Regulator INRC10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
32 Headphone V+
Pop Noise Suppression Pop Noise Suppression
OUTR
32 Headphone V+
V+
GND
CP
C4=1uF
CN
V+
Negative Voltage Regulator
Bias
3M
MUTE
R2=100k C7=1uF
VC6=10uF
GAIN 100k
REF Gain Select
(Differential input)
V+
inverted phase
Regulator INRinverted phase
INL-
C1=1uF
C10=1uF
INL+
C2=1uF
INR+
C8=1uF
OUTL
32 Headphone
Pop Noise Suppression Pop Noise Suppression
OUTR
32 Headphone
V+
V+
GND
CP
C4=1uF
CN
V+
Negative Voltage Regulator
Bias
3M
MUTE
R2=100k C7=1uF
V+
VC6=10uF
GAIN 100k
REF Gain Select
(*2): Monolithic Ceramic Capacitors (*3): V- terminal (8pin) shouldn't be tied to V+ terminal (4pin)
-8-
NJU72040
APPLICATION NOTE The NJU72040 is an audio headphone amplifier that eliminates the need for external dc-blocking output capacitors. The NJU72040 has built-in pop suppression circuitry to eliminate disturbing pop noise during power-on, power-off and mute-control. 1. Operating Principle The NJU72040 has the built-in differential input operational amplifiers, voltage inverter, pop noise suppression circuitry, gain selectable circuitry and thermal-overload protection circuitry (Fig.1). For single-ended input signals, connect inverted terminal (INL-, INR-) or non-inverted terminal (INL+, INR+) to ground through the capacitor. The voltage gain is selectable. In the differential circuitry, the setting gain is +6.4dB or +12.4dB for the RL=32. In the single-end input circuitry, the setting gain is +0.4dB or +6.4dB for the RL=32. The voltage inverter for NJU72040 eliminates the need for external dc-blocking output capacitors. The pop suppression circuitry for NJU72040 eliminates the pop noise during power-on, power-off and mute-control.
V+
inverted phase
Regulator INRC10 inverted phase
INL-
C1
INL+
C2
INR+
C8
OUTL
32 Headphone V+
Pop Noise Suppression Pop Noise Suppression
OUTR
32 Headphone V+
V+
GND
CP
C4
CN
V+
Negative Voltage Regulator
Bias
MUTE 3M
R2 C7
VC6
GAIN 100k
REF Gain Select
Fig.1 The NJU72040 functional block diagram 1.1 External parts 1.1.1 Input coupling capacitors Ci (C1, C2, C8, C10) The input coupling capacitor (Ci) and the input resistance (Rin=61k typ.) for the inverted terminal form a high-pass filter with the corner frequency determined in [fc=1/(2 x 61k x Ci)]. It is necessary to adjust 1uF or more.
-9-
NJU72040
1.1.2 Flying capacitor (C4) Use capacitors with a low-ESR (ex. ceramic capacitors) for optimum performance. Design to provide low impedance for the wiring between CP terminal (5pin), CN terminal (6pin), and the flying capacitor (C4).
CP(5pin)
C4=1uF
CN(6pin)
Fig.2 The NJU72040 block diagram (5pin, 6pin) 1.1.3 Hold capacitor (C6) Use capacitors with a low-ESR (ex. ceramic capacitors) for optimum performance. Design to provide low impedance for the wiring between the hold capacitor (C6), V- terminal (9pin) and the GND on the PCB. Separate the GND pattern connecting to the hold capacitor (C6) from that connecting to the REF terminal (8pin), thus suppressing the influence of switching noise by removing the common impedance of the GND wiring. Design no short-circuits of V- terminal (9pin) and V+ terminal (4pin) on the PCB pattern.
V-(9pin)
C6
REF(8pin)
Fig.3 The NJU72040 block diagram (8pin, 9pin) 1.1.4 Mute terminal pop noise countermeasures (C7, R2) Mute terminal needs time constant more than R2 x C7=0.1. It is necessary to adjust 100k or less.
MUTE(10pin)
R2=100k Vcnt C7=1uF
3M
Fig.4 The NJU72040 block diagram (10pin)
- 10 -
NJU72040
1.2 Control of V+ terminal and Mute terminal 1.2.2 Power-on procedure 1. Turn on the V+. 2. After 5msec from power on, change the control voltage of MUTE terminal (Vcnt) from "Low" to "High". * It is necessary to stabilize an IC for 5msec. By releasing the MUTE function, the output terminal output the signal. 1.2.3 Power-off procedure 1. Change the control voltage of MUTE terminal (Vcnt) from "High" to "Low". By the MUTE function, the output signals are stopped from output terminal. 2. Turn off the V+ after "2RC" sec from MUTE. * It is necessary to stabilize a MUTE condition for "2RC" sec. Ex.) R2=100k, C7=1uF -> 2R2 x C7=200msec
V+ (4pin)
t 5msec Vcnt 2RC=200msec
MUTE ON
MUTE OFF
MUTE ON
t
MUTE (10pin) t
Fig.5 Turn-on / Turn-off timing chart
- 11 -
NJU72040
TERMINAL DESCRIPTION
Terminal
SYMBOL
FUNCTION
V+
EQUIVALENT CIRCUIT
V+ V+
VOLTAGE
1 2 13 14
INLINL+ INRINR+
AC Input
40k
0V
V-
V-
V+
3 12
OUTL OUTR
FB
AC Output
10
5.5k
20k
0V
VREF
V-
V+
V+
V+
7
GAIN
Gain Select
2k
20k
0V
100k
VV+ V+
10
MUTE
MUTE/Pop Noise Suppression
1k
20k
0V
3M
V-
- 12 -
NJU72040
TERMINAL DESCRIPTION
Terminal
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
V+
VOLTAGE
5
CP
Flying Capacitor Positive Terminal
-
V-
6
CN
Flying Capacitor Positive Terminal
-
V40k 69k 5.5k 10
V-
INL+ INR+ V+
OUTL OUTR
8
REF
Reference Voltage Input
VV-
-
- 13 -
NJU72040
TYPICAL CHARACTERISTICS
Supply Current vs Tem perature V+=3.3V, RL=NoLoad, MUTE=L 25 25 Supply Current vs Tem perature V+=3.3V, RL=NoLoad, MUTE=H
20 Supply Current[mA] Supply Current[mA]
20
15 GAIN=L,H
15
GAIN=L,H
10
10
5
5
0 -50 -25 0 25 50
o
0 75 100 125 -50 -25 0 25 50
o
75
100
125
Temperature[ C] Supply Current vs Supply Voltage RL=NoLoad, MUTE=L, GAIN=L 25 25
Temperature[ C] Supply Current vs Supply Voltage RL=NoLoad, MUTE=H, GAIN=L
20 Supply Current[mA] Supply Current[mA]
20
15
15
10 Ta=85oC 5 Ta=25oC Ta=-40oC 0 0 0.5 1 1.5 2 2.5 3 3.5 4
10 Ta=85oC 5 Ta=25oC Ta=-40oC 0 0.5 1 1.5 2 2.5 3 3.5 4
0
Supply Voltage[V] Supply Current vs Supply Voltage RL=NoLoad, MUTE=L, GAIN=H 25 25
Supply Voltage[V] Supply Current vs Supply Voltage RL=NoLoad, MUTE=H, GAIN=H
20 Supply Current[mA]
20 Supply Current[mA]
15
15
10 Ta=85oC 5 Ta=25oC Ta=-40oC 0 0 0.5 1 1.5 2 2.5 3 3.5 4
10 Ta=85oC 5 Ta=25oC Ta=-40oC 0 0.5 1 1.5 2 2.5 3 3.5 4
0
Supply Voltage[V]
Supply Voltage[V]
- 14 -
NJU72040
Equivalent Input Noise vs Tem perature V+=3.3V, RL=32, Rg=0, MUTE=H, GAIN=L, INL+=0Vrms , INL-=0Vrms, Measure:OUTL, BW=400Hz - 22kHz 0 Equivalent Input Noise vs Tem perature V+=3.3V, RL=10k, Rg=0, MUTE=H, GAIN=L, INL+=0Vrms INL-=0Vrms, Measure:OUTL, BW=400Hz - 22kHz 0
-20 Equivalent Input Noise[dBV] Equivalent Input Noise[dBV] -50 -25 0 25 50
o
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120 75 100 125
-120 -50 -25 0 25 50
o
75
100
125
Temperature[ C] VoltageGain vs Frequency V+=3.3V, RL=32, MUTE=H, INL+=0.1Vrms INL-=0.1Vrms(inverted), Measure=OUTL
Temperature[ C] VoltageGain vs Frequency V+=3.3V, RL=10k, MUTE=H, INL+=0.1Vrms INL-=0.1Vrms(inverted), Measure=OUTL
20
20
15 VoltageGain[dB]
GAIN=H Ta=-40,25,85oC VoltageGain[dB]
15
GAIN=H Ta=-40,25,85oC
10
GAIN=L Ta=-40,25,85oC
10
GAIN=L Ta=-40,25,85oC
5
5
0 10 100 1000 Frequency[Hz] MuteLevel vs Frequency V+=3.3V, RL=32, MUTE=H, GAIN=L, INL+=0.1Vrms INL-=0.1Vrms(inverted), Measure=OUTL, Filter=Bandpass 10000 100000
0 10 100 1000 Frequency[Hz] MuteLevel vs Frequency V+=3.3V, RL=10k, MUTE=H, GAIN=L, INL+=0.1Vrms INL-=0.1Vrms(inverted), Measure=OUTL, Filter=Bandpass 10000 100000
0
0
-20
-20
-40 MuteLevel[dB] MuteLevel[dB] Ta=-40,25,85oC
-40
-60
-60
-80
-80
Ta=-40,25,85oC
-100
-100
-120 10 100 1000 Freauency[Hz] 10000 100000
-120 10 100 1000 Freauency[Hz] 10000 100000
- 15 -
NJU72040
ChannelSeparation vs Frequency V+=3.3V, RL=32, Rg=600 , MUTE=H, GAIN=L, INL+=0.1Vrms, INL-=0.1Vrms(inverted), Measure=OUTR Filter=Bandpass Ta=85oC 80 ChannelSeparation[dB] Ta=-40oC 60 ChannelSeparation[dB] Ta=25oC 80 Ta=85oC Ta=25oC Ta=-40oC ChannelSeparation vs Frequency V+=3.3V, RL=10k, Rg=600, MUTE=H, GAIN=L, INL+=0.1Vrms, INL-=0.1Vrms(inverted), Measure=OUTR Filter=Bandpass 100
100
60
40
40
20
20
0 10 100 1000 Freauency[Hz] ChannelSeparation vs Frequency V+=3.3V, RL=32, Rg=600, MUTE=H, GAIN=L INR+=0.1Vrms, INR-=0.1Vrms(inverted), Measure=OUTL Filter=Bandpass Ta=85oC 80 ChannelSeparation[dB] Ta=-40oC 60 ChannelSeparation[dB] Ta=25 C
o
0 10000 100000 10 100 1000 Freauency[Hz] ChannelSeparation vs Frequency V+=3.3V, RL=10k, Rg=600, MUTE=H, GAIN=L INR+=0.1Vrms, INR-=0.1Vrms(inverted), Measure=OUTL Filter=Bandpass 100 10000 100000
100
80 Ta=85oC 60
Ta=25oC
Ta=-40oC
40
40
20
20
0 10 100 1000 Freauency[Hz] PSRR vs Frequency V+=3.3V, RL=32, MUTE=H, GAIN=L, Vripple=0.1Vrms INL+=INR+=0Vrms, INL-=INR-=0Vrms, Measure=OUTL,OUTR Filter=Bandpass 100 Ta=-40oC 80 10000 100000
0 10 100 1000 Freauency[Hz] PSRR vs Frequency V+=3.3V, RL=10k, MUTE=H, GAIN=L, Vripple=0.1Vrms INL+=INR+=0Vrms, INL-=INR-=0Vrms, Measure=OUTL,OUTR Filter=Bandpass 100 10000 100000
80
Ta=-40oC
PSRR[dB]
PSRR[dB]
60
Ta=25oC Ta=85oC
60
Ta=25oC Ta=85oC
40
40
20
20
0 10 100 1000 Freauency[Hz] 10000 100000
0 10 100 1000 Freauency[Hz] 10000 100000
- 16 -
NJU72040
CMRR vs Frequency V+=3.3V, RL=32, MUTE=H, GAIN=L, INL+(INR+)=0.1Vrms INL-(INR-)=0.1Vrms, Measure=OUTL(OUTR), BW=Bandpass 100 CMRR vs Frequency V+=3.3V, RL=10k , MUTE=H , GAIN=L,INL+(INR+)=0.1Vrms INL-(INR-)=0.1Vrms, Measure=OUTL(OUTR), BW=Bandpass
100
80 OUTR Ta=-40,25,85oC CMRR[dB] CMRR[dB] 60
80
OUTR Ta=-40,25,85oC
60 OUTL Ta=-40,25,85oC
40
OUTL Ta=-40,25,85oC
40
20
20
0 10 100 1000 Freauency[Hz] Pow er Dissipation vs Output Pow er V+=3.3V, RL=16, MUTE=H, GAIN=L, Ta=25oC f=1kHz, Measure=OUTL, BW=400Hz to 22kHz THD+N=3% 250 Power Dissipation [mW] Power Dissipation [mW] Input=Lch,Rch 200 10000 100000
0 10 100 1000 Freauency[Hz] Pow er Dissipation vs Output Pow er V+=3.3V, RL=32, MUTE=H, GAIN=L, Ta=25oC f=1kHz, Measure=OUTL, BW=400Hz to 22kHz 10000 100000
300
300
250 THD+N=3% 200 Input=Lch,Rch 150
150 Input=Lch 100
100
Input=Lch
50
50
0 0 20 40 60 80 100
0 0 20 40 60 80 100
Output Pow er [mW/ch] Therm al Shut Dow n(SupplyCurrent) V+=3.3V , RL=32 , MUTE=H , GAIN=L 14 12 10 SupplyCurrent [A] 8 6 4 2 0 120
Output Pow er [mW/ch]
160oC ->120oC
120oC ->160oC
130
140 Temperature[ C]
o
150
160
- 17 -
NJU72040
THD+N vs Output Pow er V+=3.3V, RL=16, MUTE=H , GAIN=L Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=400Hz to 22kHz THD+N vs Output Pow er V+=3.3V, RL=32, MUTE=H, GAIN=L Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=400Hz to 22kHz
10
10
1 THD+N[%] Ta=-40 C
o
1 THD+N[%]
Ta=-40,25,85oC
0.1
Ta=25,85oC
0.1
0.01 0.001
0.01
0.1
1
10
100
1000
0.01 0.001
0.01
0.1
1
10
100
1000
Output Pow er[mW] THD+N vs Output Pow er V+=3.3V, RL=16, MUTE=H, GAIN=L, Ta=25oC Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=22Hz to 22kHz
Output Pow er[mW] THD+N vs Output Pow er V+=3.3V, RL=32, MUTE=H, GAIN=L, Ta=25oC Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=22Hz to 22kHz
10
10
1 THD+N[%]
f=100Hz,1kHz THD+N[%]
1
f=100Hz,1kHz
0.1
f=10kHz
0.1 f=10kHz
0.01 0.001
0.01
0.1
1
10
100
1000
0.01 0.001
0.01
0.1
1
10
100
1000
Output Pow er[mW] THD+N vs Output Pow er V+=3.3V, RL=16, MUTE=H , GAIN=L Input=INL+/R+,INL-/R-(inverted), f=1kHz, Measure=OUTL, BW=400Hz to 22kHz
Output Pow er[mW] THD+N vs Output Pow er V+=3.3V, RL=32, MUTE=H, GAIN=L Input=INL+/R+,INL-/R-(inverted), f=1kHz, Measure=OUTL BW=400Hz to 22kHz
10
10
1 THD+N[%]
Input=Lch , Rch THD+N[%]
1 Input=Lch , Rch
0.1
Input=Lch
0.1 Input=Lch
0.01 0.001
0.01
0.1
1
10
100
1000
0.01 0.001
0.01
0.1
1
10
100
1000
Output Pow er[mW]
Output Pow er[mW]
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NJU72040
THD+N vs Output Voltage V+=3.3V, RL=10k, MUTE=H , GAIN=L Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=400Hz to 22kHz THD+N vs Output Voltage V+=3.3V, RL=10k, MUTE=H, GAIN=L, Ta=25oC Input=INL+,INL-(inverted), AC_GND=INR+,INR-, f=1kHz Measure=OUTL, BW=22Hz to 22kHz
10
10
1 THD+N[%]
1
THD+N[%]
0.1 Ta=-40,25,85oC
0.1 f=100,1k,10kHz 0.01
0.01
0.001 0.01
0.1
1
10
0.001 0.01
0.1
1
10
Output Voltage[Vrms] THD+N vs Output Voltage V+=3.3V, RL=10k, MUTE=H, GAIN=L Input=INL+/R+,INL-/R-(inverted), f=1kHz, Measure=OUTL BW=400Hz to 22kHz
Output Voltage[Vrms] THD+N vs Output Voltage V+=3.3V, MUTE=H, GAIN=L, Ta=25oC Input=INL+,INL-(inverted), f=1kHz, Measure=OUTL , BW=400Hz to 22kHz
10
10
RL=16 1 1 RL=32 THD+N[%] THD+N[%] RL=64 0.1
0.1
Input=Lch , Rch Input=Lch
0.01
0.01
RL=1k
RL=10k 0.001 0.01 0.001 0.01
0.1
1
10
0.1 1 Output Voltage[Vrms]
10
Output Voltage[Vrms]
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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